1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of removing dummy fin structures when forming FinFET devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1a is a perspective view of a reference FinFET semiconductor device “A” that is formed above a semiconductor substrate “B.” The device A includes a plurality of fins “C,” a gate electrode “D,” sidewall spacers “E” and a gate cap layer “F.” The drawings discussed herein are cross-sectional views taken through the gate electrode D in a direction that is parallel to the long axis of the gate electrode D, i.e., in the gate width direction, indicated by the line “X-X”. In a conventional process flow, the portions of the fins C that are positioned in the source/drain regions may be increased in size or even merged together (not shown in FIG. 1A) by performing one or more epitaxial growth processes. It should be understood that FIG. 1A is only provided to show the location of various cross-sectional views that may be depicted in the drawings below.
In a FinFET device, the gate electrode D encloses both sides and an upper surface of the fins C to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fins C, and the FinFET device A only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate B so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode D of the FinFET device A, the surfaces (and the inner portion near the surface) of the fins C, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fins C with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive currents than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
One process flow that is typically performed to form FinFET devices involves forming a plurality of trenches in the substrate to define the areas where STI regions will be formed and to define the initial structure of the fins. These trenches are typically formed in the substrate during the same process operation for processing simplicity. The trenches have a target depth that is sufficient for the needed fin height and deep enough to allow formation of an effective STI region. After the trenches are formed, a layer of insulating material, such as silicon dioxide, is formed so as to overfill the trenches. Thereafter, a chemical mechanical polishing (CMP) process is then performed to planarize the upper surface of the insulating material with the top of the fins (or the top of a patterned hard mask). Thereafter, an etch-back process is performed to recess the layer of insulating material between the fins and thereby expose the upper portions of the fins, which corresponds to the final fin height of the fins.
As FinFET devices have been scaled to meet ever increasing performance and size requirements, the width of the fins has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm. Traditionally, isolation structures were always the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the semiconductor device. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching the trenches in the substrate that defined the fins.
However, as the dimensions of the fins C became smaller, problems arose with manufacturing the isolation structures before the fins C were formed. As one example, trying to accurately define very small fins C in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate B. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form a so-called “sea-of-fins” across the substrate B, and thereafter remove some of the fins where larger isolation structures will be formed. The fins that are to be removed in such a process are sometimes referred to as “dummy fins” as they are not intended to be part of the final FinFET devices that are formed on the substrate B.
FIGS. 1B-1F depict one illustrative prior art method of removing dummy fin structures when forming FinFET devices. FIG. 1B depicts an illustrative FinFET device 10 that is at the point of fabrication where the “sea-of-fins” 16 has been initially formed in the substrate 12. The plurality of fins 16 are formed by performing one or more etching processes through a patterned mask layer (not shown) to define a plurality of fin-forming trenches 14 in the substrate 12. Using this “sea-of-fins” type manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 16 to very small dimensions due to the more uniform environment in which the etching process that forms the fin-forming trenches 14 is performed. In the example depicted in FIGS. 1B-1F, the fins 16 all have a single uniform spacing. However, in a real-world device, the fins 16 may be formed so as to have various regions with different spacing or fin pitches.
After the “sea-of-fins” has been formed, some of the fins 16, i.e., the dummy fins, must be removed to create room for or define the spaces where isolation regions will ultimately be formed. FIG. 1C depicts the device 10 after several process operations have been formed. Initially, a patterned mask layer 18, e.g., a patterned photoresist mask, is formed above the substrate 10. In the depicted example, the mask layer 18 has an opening 18A that is formed so to expose an illustrative dummy fin 16X for removal, while masking the device fins 16Y that will be part of the final device 10. In the depicted example, only a single fin will be removed to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin 16 may be removed. In the example depicted in FIGS. 1C-1D, the opening 18A is precisely aligned over the dummy fin 16X that is to be removed. FIG. 1D depicts the device 10 after a timed etching process has been performed to remove the dummy fin 16X. Any etching of the substrate 12 during the dummy fin etch process is not depicted in FIG. 1D.
In some cases, with very tight fin pitches, the lithography and etching processes that are performed to remove the dummy fins 16X can result in undesirable damage to the device fins 16Y, the fins that are intended for final use in the device 10. In contrast to the idealized situation depicted in FIGS. 1C-1D, FIGS. 1E-1F depict an example where the opening 18A in the patterned mask layer 18 is somewhat misaligned. Such misalignment may occur for a variety of reasons, e.g., variations on photolithography tools, materials and techniques, overlay errors, etc. In the example depicted in FIGS. 1E-1F, the opening 18A in the misaligned patterned mask layer 18 exposes a portion of a device fin 16Y as well as a portion of the illustrative dummy fin 16X. FIG. 1F depicts an example of where an anisotropic etching process was performed through the misaligned patterned masking layer 18. In this situation, due to the misaligned patterned masking layer 18, the anisotropic etching process undesirably removes a portion of the device fin 16Y and it results in the removal of only a portion of the dummy fin 16X. Failure to remove all of the dummy fins that are intended to be removed may result in isolation regions being less effective at performing their important electrical isolation function. Removal of all or portions of device fins that are intended to be included in the final integrated circuit product can result in reduced device performance and perhaps failure.
The present disclosure is directed to various methods of removing dummy fin structures when forming FinFET devices that may solve or reduce the impact of one or more of the problems identified above.